1. Field of the Invention
The present invention relates to semiconductor integrated circuit, in particular, relates to a probe test technique for semiconductor integrated circuits.
2. Description of the Related Art
As known in the art, a large number of semiconductor chips, each designed to provide desired functions, are integrated within a semiconductor wafer in the semiconductor manufacture process. The semiconductor chips on the semiconductor wafer are tested before the dicing, which involves cutting the semiconductor wafer into the semiconductor chips. The test of the semiconductor chips is achieved by a tester and a probe card provided with test probes. Such test is often referred to as the probe test.
When a probe test is performed, test probes are placed on associated pads of semiconductor chips to provide electrical connections between the semiconductor chips and the tester. The test probes are required to be in contact with the associated pads at the same time. The probe test time is increased as the number of the semiconductor chips integrated within the semiconductor wafer is increased.
Japanese Laid Open Patent Application No. JP-A 2003-332450 discloses a semiconductor device structure for increasing the density of contact pads integrated on the semiconductor chip. In the disclosed semiconductor device structure, contact pads having different sizes are alternately arranged in line. The larger contact pads are used to be probed by test probes, and also used to be wire-bonded. The smaller pads, on the other hand, are dedicated to be wire-bonded. The semiconductor device includes first and second internal circuits, and the larger contact pads are connected with selected ones of the first and second internal circuits through switches. Additionally, the smaller contact pads are directly connected with the second internal circuits. When a probe test is performed, test probes are placed on the larger contact pads, and signals are firstly fed to the first internal circuits through the larger pads and the switches. This is followed by electrically connecting the larger contact pads with the second internal circuits, and then feeding signals to the second internal circuits. The electrical connections between the larger pads and the first and second internal circuits are controlled by a switch control circuit integrated within the semiconductor device.
Japanese Laid Open Patent Application No. 2001-77162 discloses a technique for reducing the probe test time. In the disclosed technique, a probe test is performed on multiple lines of the semiconductor chips at the same time. This application discloses that the semiconductor chips each includes a line of contact pads, and test probes are arranged in two lines on a probe card which is adapted to the parallel probe test. Such parallel probe test effectively reduces the probe test time.
However, the above-described conventional arts suffer from drawbacks as follows. The semiconductor device structure disclosed in Japanese Laid Open Patent Application No. JP-A 2003-332450 requires separately testing the first and second internal circuits. In this semiconductor device structure, for example, the test of the first internal circuits is firstly performed, and then the test of the second internal circuits is performed after the test of the first internal circuits is completed. This undesirable increases the probe test time.
The technique disclosed in the Japanese Laid Open Patent Application No. 2001-77162, on the other hand, requires all the contact pads to be probed by the testing probes, resulting in the increase in the number of the contact pads to be probed. Additionally, this technique is not adapted to a pad arrangement in which contact pads are arranged in both of horizontal and vertical directions, imposing restrictions on the pad arrangement. Such restrictions may make it difficult to design semiconductor chip.